The present invention relates to processes for selectively etching dielectric layers, for example, in the context of a dual damascene process.
The technology of fabricating semiconductor integrated circuits continues to advance in the number of transistors, diodes, capacitors and/or other electronic devices that can be fabricated on a single integrated circuit chip. This increasing level of integration is being accomplished in large part by decreasing minimum feature sizes.
Advanced integrated circuits contain multiple interconnect layers separated from the semiconductor substrate and from each other by respective dielectric layers. For instance, logic circuitry, such as that found in microprocessors, requires several interconnect layers with intervening dielectric layers. A horizontal interconnect layer is formed over one dielectric layer and then covered by another dielectric layer. Small contact or via holes need to be etched through each of the dielectric layers to connect the interconnect layers.
Several techniques are employed to create interconnect lines and vias. One such technique involves a process generally referred to as a “dual damascene process.” This process includes forming a trench and an underlying via bole, whereupon the trench and the via hole are filled with a conductor material, simultaneously forming an interconnect line and an underlying via.
One particular dual damascene process will now be described with reference to FIGS. 1A-1F, which are taken from U.S. Pat. No. 6,211,092, the entire disclosure of which is incorporated by reference. An etching structure is formed that comprises the following layers: (a) an underlying layer 10, (b) a thin lower stop layer 12, (c) a lower dielectric layer 14, (d) a thin upper stop layer 16 and (e) an upper dielectric layer 20. The stop layers 12, 16 have compositions relative to the dielectric layer 14, 20 compositions such that a selected etch process etches through the overlying dielectric layer but stops on the stop layer.
Examples of materials for the dielectric layers 14, 20 that are known in the art include doped and undoped silicon oxide materials. Undoped silicon oxide materials are typically of the formula SiOx, wherein x is between 1.4 and 2.1, with silicon dioxide (where x is approximately 2) being most prevalent. Doped silicon oxide materials are materials containing silicon, oxygen and one or more additional species. These layers can be grown, for example, by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).
Silicon nitride is a typical stop layer material where the dielectric is a silicon oxide material. Silicon nitride can be grown, for example, by CVD or PECVD.
A first photoresist layer 44 is deposited and photographically patterned to form mask apertures 46 corresponding to the via holes, only one of which is illustrated. Note that the underlying layer 10 typically includes dielectric and metal regions, with a metal region being found in the area of the hole.
In a first etch step, an extended via hole 50, as illustrated in FIG. 1B, is etched through the upper dielectric layer 20, the upper stop layer 16, and the lower dielectric layer 14 down to the lower stop layer 12. The etch chemistry is chosen to be selective such that the etch stops at the top surface 52 of the lower stop layer 12. For example, in a first step, a non-selective timed etch can be used to etch the via hole 50 through the upper dielectric layer 20, the upper nitride stop layer 16, and part of the way through the lower dielectric layer 14. A second etch step with good oxide:nitride selectivity can then be used to selectively etch the remainder of the way through the lower dielectric layer 14 and stop on the upper surface 52 of the lower stop layer 12, completing the extended via hole 50.
In an unillustrated step, the first photoresist layer 44 is stripped. Then, as illustrated in FIG. 1C, a second photoresist layer 56 is deposited and photographically patterned to form a mask aperture 58, which corresponds to the trench. In a subsequent etch step illustrated in FIG. 1D, a trench 62 is etched through the upper dielectric layer 20 down to the top surface 64 of the upper stop layer 16. The depth of the extended via hole 50 is thereby effectively reduced to form via hole 50′.
In a further etch step, the exposed portion of the lower stop layer 12 at the bottom of the via hole 50′ is etched, as illustrated in FIG. 1E, through the lower stop layer 12 and down to an upper surface 68 of the underlying layer 10, which is typically a metal surface, at least at the position of the via hole 50′. Depending upon the compositions of the two stop layers 12, 16, this etch step may remove portions of the upper stop layer 16 exposed at the bottom of the trench 62 to expose an upper surface 70 of the lower dielectric layer 14. In another step, performed either before or after this etch step, the second photoresist layer 56 is stripped along with any sidewall polymer formed in the dielectric etch.
Thereafter, as illustrated in FIG. 1F, a metal 72 is filled into the trench 62 and the underlying via hole 50′ to contact the upper surface 68 of the underlying layer 10. Subsequent chemical mechanical polishing (CMP) removes any metal overflowing the trench. The metal 72 forms both a horizontal interconnect line 74 as well as a via 76, which contacts the underlying layer 10. The metal 72 is preferably copper, but can be another metal such as aluminum. However, the dual-damascene process is particularly applicable to copper metallization because no copper etching is required.
It is generally desirable for the dielectric constant k of the non-metallic materials used within the dual damascene structure to be as low as possible. For example, a reduced dielectric constant k results in reduced capacitance, which in turn reduces cross-talk and coupling, allowing for increased operating speeds. Unfortunately, the materials that are typically used in connection with the stop layers 12, 16 (e.g., silicon nitride) are relatively high-dielectric-constant k materials. For example, the dielectric constant k for Si3N4 is about 7.5. (This is to be contrasted, for example, with the dielectric constant k of silicon dioxide, which is typically between 3.9 and 4.2.)
Hence, there is a need in the art for a dual damascene structure in which the adverse impact of such relatively high dielectric constant k materials is reduced.